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MP7612
...the analog plus company TM
FEATURES * Eight Independent 12-Bit DACs with Output Amplifiers * Low Power 320 mW (typ.) * Serial Digital Data and Address Port (3-Wire Standard) * 12-Bit Resolution, 11 Bit Accuracy * Extremely Well Matched DACs * Extremely Low Analog Ground Current (<60A/Channel) * +10 V Output Swing with +11.4 V Supplies * Zero Volt Output Preset (Data = 10 .. 00) * Rugged Construction - Latch-Up Free * Parallel Version: MP7613
Octal 12-Bit DAC ArrayTM D/A Converter with Output Amplifier and Serial Data/Address P Control Logic
APPLICATIONS * * * * * * * Data Acquisition Systems ATE Process Control Self-Diagnostic Systems Logic Analyzers Digital Storage Scopes PC Based Controller/DAS
April 1996-4
GENERAL DESCRIPTION
The MP7612 provides eight independent 12-bit resolution Digital-to-Analog Converters with voltage output amplifiers and a 3-wire standard serial digital address and data port. Typical DAC matching for B grade versions is 0.7 LSB across all codes. Accuracy of +0.75 LSB for DNL and +1 LSB for INL is also achieved for B grades. The output amplifier is capable of
sinking and sourcing 5mA, and the output voltage settles to 12-bits in less than 30s (typ.). The MP7612 is equipped with a serial data (3-wire standard)
-processor logic interface to reduce pin count, package size,
and board space. Built using an advanced linear BiCMOS, these devices offer rugged solutions that are latch-up free, and take advantage of EXAR's patented thin-film resistor process which exhibits excellent long term stability and reliability.
SIMPLIFIED BLOCK DIAGRAM
VRP
- +
VRP VRN
D Q 12 DAC0 LAT0 XR XE + -
VO0
RST XE0 - XE7
LD 12
VRN
XE0
Not Used
8
8 D Q LAT7 XR XE XE7 12
VRP
DAC7 + -
4 to 16 Decoder SDI LD CLK
EN D LAT Q LAT D Q EN 4
VO7
VRN
D0 to D11 A0 to A3 16-Bit Shift Register VRP VEE VEE VCC VCC AGND AGND VREF DGND DVDD
Tri-State Buffer SDO LD
Rev. 3.00
E1996
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z FAX (510) 668-7010
MP7612
ORDERING INFORMATION
Package Type
PLCC PLCC SOIC SOIC
Temperature Range
-40 to +85C -40 to +85C -40 to +85C -40 to +85C
Part No.
MP7612BP MP7612AP MP7612BS MP7612AS
Res. (Bits)
12 12 12 12
INL (LSB)
1 2 1 2
DNL (LSB)
0.75 1 0.75 1
FSE (LSB)
6 8 6 8
PIN CONFIGURATIONS
1
See the following page for pin descriptions
AGND VO0 VO1 VO2 VO3 VEE VCC VREF VCC VEE VO4 VO5 VO6 VO7
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
DGND N/C N/C DVDD DGND N/C SDO SDI CLK LD N/C RST N/C AGND
44 Pin PLCC
28 Pin SOIC (Jedec, 0.346")
Rev. 3.00 2
MP7612
PIN DESCRIPTION
SOIC Pin #
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 1, 8, 10, 11, 14, 16, 17, 22, 23, 25, 27, 28, 30, 33, 35, 36, 38, 39, 41, 42, 43 44 37 40 29 31 32 34 26
PLCC Pin #
2 3 4 5 6 7 9 12 13 15 18 19 20 21 24
Symbol
AGND VO0 VO1 VO2 VO3 VEE VCC VREF VCC VEE VO4 VO5 VO6 VO7 AGND N/C RST N/C LD CLK SDI SDO N/C DGND DVDD N/C N/C
Description
Analog Ground DAC 0 Output DAC 1 Output DAC 2 Output DAC 3 Output Analog Negative Power Supply (-12 V) Analog Positive Power Supply (+12 V) Voltage Reference Input (+5 V) Analog Positive Power Supply (+12 V) Analog Negative Power Supply (-12 V) DAC 4 Output DAC 5 Output DAC 6 Output DAC 7 Output Analog Ground No Connection Reset all DACs to 0 V Output No Connection Load Signal; Load Data to Selected DAC Serial Data Clock Serial Data Input Shift Register Serial Output No Connection Digital Ground Digital Positive Power Supply (+5 V) No Connection No Connection
28
DGND
Digital Ground
Rev. 3.00 3
MP7612
ELECTRICAL CHARACTERISTICS VCC = +12 V, VEE = -12 V, VREF = 5 V, DVDD = 5.0 V, T = 25C, Output Load = 5k (unless otherwise noted)
25C Typ Tmin to Tmax Min Max
Parameter STATIC PERFORMANCE Resolution (All Grades) Integral Non-Linearity (Relative Accuracy) A B Differential Non-Linearity A B Positive Full Scale Error A B Negative Full Scale Error A B Bipolar Zero Offset A B INL Matching A B All Channels Maximum Error with DAC 0 adjusted to minimum error A B Bipolar Zero Matching A B Full Scale Error Matching A B DYNAMIC PERFORMANCE Voltage Settling from LD to VDAC Out1 Channel-to-Channel Crosstalk1, 6 Digital Feedthrough1, 6 Power Supply Rejection Ratio REFERENCE INPUTS Impedance of VREF VREF Voltage1, 2
Symbol
Min
Max
Units
Test Conditions/Comments
N INL
12
Bits LSB 2 1 2 1 LSB 1 0.75 1 0.75 LSB 6 4 8 6 8 6 4 3 8 6 LSB 6 4 8 6 LSB 4 3 LSB 2 1.5 2 1.5 LSB End Point Linearity Spec
DNL
+FSE
-FSE
ZOFS
INL
ME
4 2 ZOFS 4 3 FSE 4 3
4 2 LSB 4 3 LSB 4 3
tsd CT Q PSRR
30 0.04 -70
50
50
sec LSB dB ppm/%
ZS to FS (20 V Step) DC CLK and Data to VOUTi VEE & VCC = +5%, ppm of FS
5
REF VREF
350 3.5
700
1.05k 6
350
1.05k
V
See Application Hints for driving the reference input
Rev. 3.00 4
MP7612
ELECTRICAL CHARACTERISTICS (CONT'D)
25C Typ Tmin to Tmax Min Max Parameter DIGITAL INPUTS3 Logic High Logic Low Input Current Input Capacitance1 ANALOG OUTPUTS Output Swing Output Drive Current Output Impedance Output Short Circuit Current -VEE +1.4 -5 RO ISC VCC -1.4 5 1 25 30 40 55 V mA mA mA mA mA VIH VIL IL CL 2.4 0.8 +10 8 V V A pF Symbol Min Max Units Test Conditions/Comments
+FS to AGND +FS to VEE -FS to AGND -FS to VCC
DIGITAL OUTPUTS Output High Voltage Output Low Voltage POWER SUPPLIES VCC Voltage5 VEE Voltage5 DVDD Voltage Positive Supply Current Negative Supply Current Digital Supply Current Power Dissipation ANALOG GROUND CURRENT Per Channel1 DIGITAL TIMING SPECIFICATIONS1,4 Input Clock Pulse Width Data Setup Time Data Hold Time CLK to SDO Propagation Delay DAC Register Load Pulse Width Preset Pulse Width Clock Edge to Load Time LD Falling Edge to SDO Tri-state Enable LD Rising Edge to SDO Tri-state Disable LD Rising Edge to CLK Enable LD Set-up Time with Respect to CLK tCH, tCL tDS tDH tPD tLD tPR tCKLD1 tCKLD2 tHZ1 tHZ2 tLDCK tLDSU 35 15 15 40 35 50 140 0 50 50 50 30 ns ns ns ns ns ns ns ns ns ns ns IAGND 60 A See Application Notes VCC VEE DVDD ICC IEE IDD PDISS VREF+1.5 12 -12.75 -12 4.5 5 8 15 320 12.75 -5 5.5 10 20 2 420 VREF+1.5 12.75 -12.75 -5 4.5 5.5 10 20 2 450 V V V mA mA mA mW VOH VOL 4.5 0.5 V V
Bipolar zero Bipolar zero Bipolar zero Bipolar zero
VIL = 0, VIH = 5.0, CL = 20 pF
Note: tLD and tCKLD2 cannot both be min. since tCKLD1=tCKLD2+tLD
Rev. 3.00 5
MP7612
ELECTRICAL CHARACTERISTICS (CONT'D)
NOTES: 1 Guaranteed; not tested. 2 Specified values guarantee functionality. 3 Digital inputs should not go below digital GND or exceed DVDD supply voltage. 4 See Figures 2 and 3. All digital input signals are specified with tR = tF = 10 ns 10% to 90% and timed from a 50% voltage level. 5 For power supply values < 2VREF, the output swing is limited as specified in Analog Outputs. 6 Digital feedthrough and channel-to-channel crosstalk are heavily dependent on the board layout and environment. Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS (TA = +25C unless otherwise noted)1, 2 VCC to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . +16.5 V VEE to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . -16.5 V DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . +6.5 V VREF to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1 V (Functionality guaranteed for 0.5 V only) Digital Input & Output Voltage to DGND -0.5 to DVDD +0.5V Analog Inputs & Outputs . . . . . . . Indefinite Shorts to VCC, VEE, DVDD, AGND, DGND (provided that power dissipation of the package spec is not exceeded) Operating Temperature Range Extended Industrial . . . . . . . . . . . . . . -40C to +85C Maximum Junction Temperature . . . -65C to 150C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 150C Lead Temperature (Soldering, 10 sec) . . . . . +300C Package Power Dissipation Rating @ 75C SOIC, PLCC . . . . . . . . . . . . . . . . . . . . . . . . 1150mW Derates above 75C . . . . . . . . . . . . . . . . . 15mW/C
NOTES: 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100s.
APPLICATION NOTES Refer to Section 8 in the 1995 Data Acquisition products Databook for Applications Information
NOTE: When using these DACs to drive remote devices, the accuracy of the output can be improved by utilizing a remote analog ground connection. The difference between the DGND and AGND should be limited to 300 mV to assure normal operation. If there is any chance that the AGND to DGND can be greater than 1 V, we recommend two back-to-back diodes be used between DGND and AGND to clamp the voltage and prevent damage to the DAC. Using a buffer between the remote ground location and AGND may help reduce noise induced from long lead or trace lengths.
Rev. 3.00 6
MP7612
SDI 1 (Data In) 0 CLK 1 0 1 0 1 0 DAC Register Loaded A3 (1) MSB A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D0
LD
SDO
Previous Data
VOUT Notes: (1) Because A3 is available immediately after 16th clock edge of DATA Shift-in, only 15 clock cycles are needed to complete the readback.
Figure 1. Serial Data Timing and Loading
SDI
1 0
tDS
tDH SDO 1 0 CLK 1 0 tCL LD 1 0 tCH tPD tCKLD2
tHZ1
tHZ2 HIGH Z tLDCK
tLDSU
tCKLD1
tLD +FS VOUT -FS tSD +1/2 LSB Band Notes: (1) CLK should be high during the falling edge of LD to insure proper function of the shift register.
Figure 2. Serial Data Input Timing (RST = "1")
RST 1 0 VOUT VOUT = 0 V
tPR
Note: Reset settling time is +1/2 LSB Error Band
Figure 3. Reset Operation
Rev. 3.00 7
MP7612
The MP7612 is equipped with a serial data (3-wire standard)
-processor logic interface to reduce pin count, package size,
and board wire (space). If the LD signal is high, the CLK signal loads the digital input bits (SDI) into the shift register (4 bits address A3 to A0 plus 12 bits data DB11 to DB0 for the MP7612). The LD signal going low loads the data into the selected DAC. Function Shift Data In and Out Stop Shifting Data In and Out Load DACs DAC 0 DAC 1 DAC 2 DAC 3 DAC 4 DAC 5 DAC 6 DAC 7 A3 X X A2 A1 A0 X X X X X X LD 1 0
The LD signal going low also disables the serial data (SDI), output (SDO 3-stated) and the CLK input. This design tremendously reduces digital noise and glitch transients into the DACs due to free running CLK and SDI. Note also that the preset signal (RST) resets all analog outputs to 0 volt regardless of digital inputs. CLK 01
Repeat
RST 1 1
SDI Data Input Valid X
SDO Data Output Valid Hi-Z
X
0 0 0 0 0 0 0 0 1
0 0 0 0 1 1 1 1 0
0 0 1 1 0 0 1 1 0
0 1 0 1 0 1 0 1 0
No Operation 10 10 10 10 10 10 10 10 No Operation No Operation No Operation X
1 1 Reset all DACs to 0 V X
1 1 X
1 1 X
0 1 X
X X X X X X X X X X X X X X
1 1 1 1 1 1 1 1
X X X X X X X X
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
1 1 0
X X X
Hi-Z Hi-Z X
Table 1. Digital Function Truth Table Serial In/Serial Out Note: For timing information see Electrical Characteristics
Rev. 3.00 8
MP7612
Hex Code 000 Binary Code 000000000000 Output Voltage = 2 * Vr (-1 + 2*D ) 4096 (Vr = +5 V) 10 * (-1 + 0) = -10
7FF 800 801
011111111111 100000000000 100000000001
10 * (-1 +
4094 ) = -4.88 mV 4096 4096
10 * (-1 + 4096 ) = 0 10 * (-1 + 4098 ) = 4.88 mV 4096
FFF
111111111111
10 * (-1 + 8190 ) = 9.99512
4096
Table 2. MP7612 Ideal DAC Output vs. Input Code Note: See Electrical Characteristics for real system accuracy
SERIAL INTERFACE DIAGRAMS
Rev. 3.00 9
MP7612
VRI1 1 8 VOI1 VRI2 1 VOI2 8 VRIn 1 VOIn 8
IC(1)
IC(2)
SDI LD SDO
IC(n)
SDI LD SDO
PC
Data LD CLK
SDI LD
SDO
Figure 4. Simplified Diagram
VRI1 1 8
VOI1
VRI2 1 8
VOI2
VRIm 1 8
VOIm
IC(1)
IC(2)
SDI LD SDO
IC(n)
SDI LD SDO
PC
Data Out Data CS or LD CLK n
SDI LD
SDO
#1
#2
#n
Figure 5. Simplified Diagram
VRI1 VOI1
VRI2 VOI2
VRIn VOIn
1 SDO Address Address Decoder n 2
IC(1)
2n
SDI LD SDO1
IC(2)
SDI LD SDO2
IC(n)
SDI LD SDOm
PC
WR (SDI) Data In CLK
Figure 6. Simplified Diagram
Rev. 3.00 10
MP7612
16 A0 to A15 3 E1 02 R/W DBO to DB7 8 E3 E2 A0 to A2 74LS138 Address Decoder 8 Data Bus 16 Address Bus
MC6800
LD DB7 SDI RST
CLK
From SYSTEM RESET NOTES 1. Execute consecutive memory write instructions while manipulating the data between WRITEs so that each WRITE presents the next bit. 2. The serial data loading is triggered by the CLK pulse which is asserted by a decoded memory WRITE to memory location 2000, R/W, and 02. A WRITE to address 4000 transfers data from input shift register to DAC register.
Figure 7. MC6800 Interface
8
Address Bus 8 +5 E1 E3 3 A0 to A2 74LS138 Address Decoder
8085
ALE
8212
WR 8 SOD Data Bus
E2
LD SDI RST
CLK
From SYSTEM RESET NOTES: 1. Clock generated by WR and decoding address 8000. 2. Data is clocked in the DAC shift register by executing memory write instructions. The clock input is generated by decoding address 8000 and WR. Data is then loaded into the DAC register with a memory write instruction to address 4000. 3. Serial data must be present in the right justified format in registers H & L of the microprocessor.
Figure 8. 8085 Interface
Rev. 3.00 11
MP7612
PERFORMANCE CHARACTERISTICS
11 V
0V
-11 V VOUT 2.5mV
0V
-2.5mV VOUT Settling 50s/Division
Graph 1. Typical Output Settling Characteristic VREF = 5 V, RL = 5K, CL = 500pF
Graph 1 shows the typical output settling characteristic of the MP7610 Family for a RESET !ZS!FS!ZS series of code transitions. The top graph shows the output voltage transients, while the bottom graph shows the difference between the output and the ideal output.
Graph 2. Linearity with VREF = 5 V, All DACs, All Codes
Rev. 3.00 12
MP7612
Graph 3. DAC 0 INL vs. VREF
Graph 4. DAC 0 DNL vs. VREF
Graph 5. DAC 0 Linearity with VREF = 5 V, VOUT = 10
Graph 6. DAC 0 Linearity with VREF = 4.5 V, VOUT = 9
Graph 7. DAC 0 Linearity with VREF = 4 V, VOUT = 8
Rev. 3.00 13
Graph 8. DAC 0 Linearity with VREF = 3.5 V, VOUT = 7
MP7612
VOUT 50W VO
MP7610 Family
5k
500pF
CL
I
2mA
CL = 500pF, 5nF, 50nF, 500nF
Figure 9. Circuit for Determining Typical Analog Output Pulse Response
2.0mA
I
0.0 400mV
VO
-400mV 200mV CL = 500pF CL = 5nF
CL = 50nF
CL = 500nF
VOUT
-200mV 0s 1.0s 2.0s 3.0s 4.0s 5.0s 6.0s
Graph 9. Typical Response of the MP7610 Family Analog Output to a Current Pulse with CL=500pF, 5nF, 50nF, 500nF (See Figure 9. above)
Rev. 3.00 14
MP7612
44 LEAD PLASTIC LEADED CHIP CARRIER (PLCC)
D D1 2 1 44 45 x H2 45 x H1
C
Seating Plane A2
B1
D
D1
D3
BD 2
e
R D3 A1 A
INCHES SYMBOL A A1 A2 B B1 C D D1 D2 D3 e H1 H2 R MIN 0.165 0.090 0.020 0.013 0.026 0.008 0.685 0.650 0.590 MAX 0.180 0.120 ---. 0.021 0.032 0.013 0.695 0.656 0.630
MILLIMETERS MIN 4.19 2.29 0.51 0.33 0.66 0.19 17.40 16.51 14.99 MAX 4.57 3.05 --- 0.53 0.81 0.32 17.65 16.66 16.00
0.500 typ. 0.050 BSC 0.042 0.042 0.025 0.056 0.048 0.045
12.70 typ. 1.27 BSC 1.07 1.07 0.64 1.42 1.22 1.14
Note: The control dimension is the inch column
Rev. 3.00 15
MP7612
28 LEAD SMALL OUTLINE (350 MIL JEDEC SOIC)
D
28
15
E
1 14
H
C Seating Plane e B A1 L A
INCHES SYMBOL A A1 B C D E e H L MIN 0.093 0.004 0.013 0.009 0.706 0.340 MAX 0.104 0.012 0.020 0.013 0.718 0.350
MILLIMETERS MIN 2.35 0.10 0.33 0.23 17.93 8.64 MAX 2.65 0.30 0.51 0.32 18.24 8.89
0.050 BSC 0.460 0.016 0 0.485 0.050 8
1.27 BSC 11.68 0.40 0 12.32 1.27 8
Note: The control dimension is the millimeter column
Rev. 3.00 16
MP7612 Notes
Rev. 3.00 17
MP7612 Notes
Rev. 3.00 18
MP7612 Notes
Rev. 3.00 19
MP7612
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1993 EXAR Corporation Datasheet April 1996 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 3.00 20

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